1. Field of the Invention
This invention relates to electronic circuits and, more particularly, to flip-flop and other logic circuits, which are operable at low power supply voltages (e.g., less than about 1.8 volts) and have SET and/or RESET functionality.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Many electronic systems now use supply voltages that fall significantly below the conventional 5.0 volt standard. The demand for reduced power dissipation and battery requirements (e.g., in applications such as wireless and personal computing) has motivated designers to scale the supply voltage of digital circuits down from the 5.0 volt standard to about 3.3 volts, 2.5 volts, and in some cases, 1.8 volts or lower. This trend is augmented by the fact that faster silicon devices generally have lower breakdown voltages, which in turn, require lower supply voltages if device dimensions are to be scaled down. However, it is often difficult to preserve high-speed operation at low supply voltages, especially as voltages fall below approximately 1.8 volts.
Emitter-Coupled Logic (ECL) technology is often used for implementing high-speed logic circuits. ECL circuits generally differ from Metal-Oxide Semiconductor (MOS) circuits by using Bipolar Junction Transistors (BJTs) instead of Field Effect Transistors (FETs). Another difference lies in the manner in which the transistors are operated. For example, MOSFET transistors are usually operated in saturation, and therefore, demonstrate a relatively large voltage swing between transistor “on” and “off” states. To increase operating speeds, the bipolar transistors of an ECL circuit are typically configured for operating in the linear region preceding the saturation region. For example, a relatively constant current can be maintained at the emitter terminal of a bipolar transistor, so that the transistor may operate in a “current mode.” The current mode of operation provides relatively fast switching speeds by eliminating saturation mode operation and reducing the voltage swing between transistor “on” and “off” states. Logic circuits that operate in the current mode may be alternatively known as Current Mode Logic (CML).
A flip-flop is one example of a circuit that may be implemented with ECL (or CML) logic gates. In some cases, a flip-flop circuit may be implemented with a pair of cross-coupled NAND or NOR logic gates. Each of the cross-coupled logic gates may include a plurality of transistors, two or more of which may be arranged in a stacked configuration. In operation, the flip-flop circuit may receive a pair of inputs for generating a pair of complementary outputs, normally labeled “Q” and “Qbar.” When the flip-flop changes states, both Q and Qbar will correspondingly change states. When one output changes to a logic high (e.g., a logic “1”) state, the other output will change to a logic low (e.g., a logic “0”) state, and vice versa. In some cases, a clocking signal may be supplied to the flip-flop, so that all logic state changes are synchronized to occur on a rising or falling transition of a clock pulse.
If the pair of inputs supplied to the cross-coupled logic gates are labeled “SET” and “RESET,” the flip-flop may be referred to as a SET/RESET (or SR-type) flip-flop. In some cases, an SR-type flip-flop may be “set” when Q=1 and Qbar=0, and “reset” when Q=0 and Qbar=1. As such, an SR-type flip-flop may change states upon sensing a change in state at the S or R inputs (asynchronous to the clock pulse input to the flip-flop), and may store the results of the change until the opposite input is clocked out by the rising/falling transition of the clock source. The process of changing the flip-flop to the Q=1, Qbar=0 state may be referred to as “setting” the flip-flop, whereas the process of changing the flip-flop to the Q=0, Qbar=1 state may be referred to as “resetting” the flip-flop. The opposite may be true in other cases. Due to it's asynchronous SET/RESET capability, this type of SR flip-flop is often used within one or more components of a phase locked loop (PLL) device, such as a phase frequency detector (PFD), frequency divider or programmable counter. An asynchronous SR flip-flop may also be used in other, more general logic designs.
Another type of flip-flop with SET and RESET functionality is commonly referred to as a Delay (or D-type) flip-flop. The D-type flip-flop may also be referred to as a Data flip-flop. In some cases, the D-type flip-flop may be implemented by placing an inverter at the R input of an SR-type flip-flop. Since the S and R inputs of a D-type flip-flop are always in opposite states, the Q output of the D-type flip-flop will track the state of the data present at the D input. D-type flip-flops are often used to form registers. For example, several D-type flip-flops may be connected in series to form shift registers, or in parallel to form data storage registers. D-type flip-flops may also be used within one or more components of a phase-locked loop (PLL) device. For example, one or more D-type flip-flops may be included within a phase frequency detector, frequency divider or programmable counter. Like the SR flip-flop, the D-type flip-flop can also be used in general logic designs.
FIG. 1 illustrates one example of a conventional D-type flip-flop circuit 100. Flip-flop circuit 100 generally includes master portion 110 and slave portion 120. In FIG. 1, master portion 110 and slave portion 120 each include a plurality of bipolar junction transistors (BJTs), and more specifically, six NPN transistors arranged between a power supply node (VPWR) and a ground node (GND). Within master portion 110, differential transistors N1 and N2 are configured for receiving a pair of differential input signals (“D” and “Dbar”) and generating a pair of complementary values (“Z” and “Zbar”). The pair of complementary values are latched by differential transistors N3 and N4 during a clock transition, e.g., from low to high. Slave portion 120, which is configured similar to master portion 110, is coupled in series with the master portion for receiving the pair of complementary values (“Z” and “Zbar”) latched from the master portion. The output signals, Q and Qbar, from slave portion 120 are set by differential transistors N7 and N8. During the next clock transition, e.g., from high to low, the D and Dbar signals input to master portion 110 are enabled and the Q and Qbar outputs are latched by differential transistors N9 and N10.
A principle difficulty in scaling the supply voltage of digital bipolar circuits (e.g., those using ECL/CML technology) is that the “turn on” potential, e.g., the base-emitter voltage (VBE) of NPN transistors, does not scale linearly with technology. In other words, the base-emitter voltage may be expressed as:VBE≈VT ln(IC/IS)  EQ. 1where VT=kT/q, IC is the collector current, and IS is the reverse saturation current. In practice, the current density (IC/IS) of bipolar transistors has either remained constant or increased, leading to a similar trend for the base-emitter voltage (VBE). In current technology, the VBE of a typical NPN transistor may be approximately equal to 0.9 volts.
In order to accommodate low supply voltages (e.g., less than about 1.8 volts), any current path extending between the power supply and ground nodes within a bipolar circuit must include no more than one base-emitter junction. In other words, each current path between power and ground must include no “stacked” input transistors. As used herein, two input transistors are said to be “stacked” if the emitter terminal of one transistor is connected to the collector terminal of another transistor. Because the base-emitter junctions of the stacked transistors each produce a voltage drop of approximately 0.9 volts, a substantially larger supply voltage (e.g., substantially greater than 1.8 volts) must be supplied to the flip-flop circuit to avoid driving the stacked transistors into deep saturation. As noted above, ECL circuits usually avoid operating in the saturation region to avoid the reduced operating speed that occurs when operating in saturation.
As shown in FIG. 1, flip-flop circuit 100 contains two levels of bipolar junction transistors (BJT) within several of the current paths extending between the power supply (VPWR) and ground (GND) nodes. Because of it's two level (i.e., stacked) architecture, flip-flop circuit 100 cannot operate at relatively low supply voltages. For the purpose of this disclosure, a “relatively low supply voltage” will be interpreted as a supply voltage of approximately 1.8 volts or lower. Therefore, one disadvantage of flip-flop circuit 100 is the high power supply requirement necessitated by it's two level BJT architecture. For example, the minimum supply voltage needed to operate flip-flop circuit 100 may be expressed as:VPWRmin≈IR+2VBE+VCi  EQ. 2where IR is the swing voltage, or the IR (current times resistance) drop over one of the pull up resistors (R1, R2, R3 or R4), VBE is the base-emitter voltage of an NPN transistor, and VCi is the voltage drop across one of the current sources (C1 or C2). In one exemplary embodiment, the minimum supply voltage of flip-flop circuit 100 may be approximately 2.4V, assuming a base-emitter voltage (VBE) of 0.9V, a swing voltage of 300 mV and a voltage drop of 300 mV across the current source.
Due to its high power supply requirement (e.g., about 2.4 volts), flip-flop circuit 100 cannot be used within low power supply circuits, such as those requiring less than about 1.8 volts. Flip-flop circuit 100 also fails to provide SET/RESET capability, and therefore, cannot be used within circuits or devices requiring such functionality (e.g., PFD circuits). As another potential disadvantage, the voltage level of one or more signals input to flip-flop circuit 100 may be substantially different from the voltage level of the output signals generated by flip-flop circuit 100. In other words, problems may arise when input signals with CMOS voltage swings (e.g., CLK/CLKbar) are supplied to a flip-flop circuit that generates output signals with ECL/CML voltage swings (e.g., “Q” and “Qbar”). For example, differences between input and output voltage swings may prohibit the use of auto-routing devices, which are often used for electrically connecting circuit components on a semiconductor chip. If large CMOS voltage swings are supplied to the second stage input, they may cause the base collector junction diode to become forward biased, thereby killing the switching function of differential transistors N7 and N8.
For at least these reasons, a need remains for an improved flip-flop circuit that can be used with relatively low supply voltages. In a preferred embodiment, the improved flip-flop circuit may include SET and/or RESET functions to allow the flip-flop circuit to be used within applications requiring such functionality. In addition, means may be included for limiting the voltage swing of one or more input signals supplied to the improved flip-flop circuit. Such means may be included, e.g., to improve the operating speed and/or enable the use of auto-routing devices when incorporating the flip-flop onto a semiconductor chip.